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The setup and hold timing parameters are ADDRHOLD in the EBI_ADDRTIMING register, RDHOLD
and RDSETUP in the EBI_RDTIMING register and WRHOLD and WR SETUP in the EBI_WRTIMING
register. Writing a value m to one of these bitfields results in a duration of the corresponding state of m
cycles. If these parameters are set to 0, it effectively means that the state is skipped.
Table 14.1 (p. 138) shows typical settings for timing.
Table 14.1. EBI Timing
Reference
t ALS
Parameter
Address Setup
Min
Typical
1
Max
Unit
t CORE_PERIOD
before ALE high
t ALH
Address Hold after
1
t CORE_PERIOD
ALE high
t ALW
t ARS
ALE Width
Address Setup
1
1
t CORE_PERIOD
t CORE_PERIOD
before RE high
t ARH
Address Hold after
1
t CORE_PERIOD
RE high
t RW
Data Read Strobe
1
t CORE_PERIOD
Width
t DRS
Data Setup before
50
ns
RE high
t DRH
Data Hold after RE
0
ns
high
t AWS
Address Setup
1
t CORE_PERIOD
before WE low
t AWH
Address Hold after
1
t CORE_PERIOD
WE high
t DWS
Data Setup before
1
t CORE_PERIOD
WE high
t DWH
Data Hold after
1
t CORE_PERIOD
WE high
t WW
Data Write Strobe
1
t CORE_PERIOD
Width
t CH
Chip Select Hold
1
t CORE_PERIOD
after WE / RE high
t CRS
Chip Select Setup
0
t CORE_PERIOD
to RE low
t CWS
Chip Select Setup
1
t CORE_PERIOD
to WE low
14.3.5 Data Access Width
It is important that the setting of the data width of the external device is respected. If the width of a
request does not match the data width specified in the MODE field of the EBI_CTRL register, a bus
fault is generated.
14.3.6 Bank Access
The EBI is split in 4 different address regions, each connected to an individual EBI_CSn line. When
accessing one of the memory regions, the corresponding CSn line is asserted. This way up to 4 separate
2011-04-12 - d0001_Rev1.10
138
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